[sebhc] h17 and h8d disk images

[Dave Dunfield]

At 18:55 01/09/2004 -0400, you wrote:
>I believe that NorthStar DOS (the original single density one) did use
>headers.  I disassembled that OS, and my source code, fully commented, from
>1978, is on Howard's site.

Hi Barry,

I beg to differ - NS 'SD' dos actually calls the controller ROM for disk
operations, (which redirects write and verify back to the DOS code)

Here is the relavent snippet for the controller ROM code for a READ
operation:

(Note that the "wait for the right sector" function occurs BEFORE it vectors
back to DOS, so this code does apply to ALL disk operations.

... Entry/motor on etc. code snipped ...

E934 CD 64 E9            CALL $E964         ; Step to track
E937 C1                  POP  B             ; <[210A] Sector/function

Here we wait for the sector to "come around" we do this by reading
the hardware register at $EB30, which is the 'B' status, and reflects
a hardware counter in the controller which counts index pulses. There
are NO data transfers ($EB50) while waiting for the right sector (hence
no header information written on the disk).

E938 CD CE E9            CALL $E9CE         ; Wait one sector time
E93B 3A 30 EB            LDA  $EB30         ; Read B status
E93E E6 0F               ANI  $0F           ; Save only sector number
E940 B8                  CMP  B             ; Are we at sector
E941 C2 38 E9            JNZ  $E938         ; No, wait for it
E944 E1                  POP  H             ; <[210C] Ram address
E945 0D                  DCR  C             ; Test function
E946 FA 0A 20            JM   $200A         ; 00=Write    \_ Redirect back to DOS
E949 C2 07 20            JNZ  $2007         ; !01=Verify  /

; Read block of data from drive

Here we wait for the "body" indicator which means that data is available -
still no actual data transfer from the drive

E94C 06 8C               MVI  B,$8C         ; Timeout count
E94E 11 50 EB            LXI  D,$EB50       ; Read data      <= Data register address
E951 0E 00               MVI  C,$00         ; Read 256 bytes <= Sector size
E953 3A 10 EB            LDA  $EB10         ; Get status
E956 E6 04               ANI  $04           ; Wait for Body
E958 C2 AE E9            JNZ  $E9AE         ; Body - ready for data
E95B 05                  DCR  B             ; Reduce timeout
E95C C2 53 E9            JNZ  $E953         ; Wait for it
E95F 3E 01               MVI  A,$01         ; Report TIMEOUT error
E961 C3 AB E9            JMP  $E9AB         ; And exit

... intervening code snipped ...

Here is the FIRST time we read the data register, and we read it exactly
256 times while stuffing the data in memory (one sectors worth), and one
more time to get the check value - we never read any other data (header)
from the disk (Search the entire disassembly, and the only reference to
the data register is the LXI D which occurs above.

;
; Read data sector from disk
;
E9AE 41                  MOV  B,C       ; Zero checkval
E9AF 1A                  LDAX D         ; Read data byte
E9B0 77                  MOV  M,A       ; Write to RAM
E9B1 A8                  XRA  B         ; Compute
E9B2 07                  RLC            ; Check
E9B3 47                  MOV  B,A       ; Resave check
E9B4 23                  INX  H         ; Next RAM address
E9B5 0D                  DCR  C         ; Reduce count
E9B6 C2 AF E9            JNZ  $E9AF     ; Read them all
E9B9 1A                  LDAX D         ; Read check value
E9BA A8                  XRA  B         ; Does it match?
E9BB CA C4 E9            JZ   $E9C4     ; Yes, it's OK


I have the N* sd controller documentation, including theory of operation
and schematics on my site, you can read through to see how the system
works. A couple of points to note:


Page 13 "Data Format"

  Zeros            16 bytes
  Sync Char(FB)     1 byte
  Data            256 bytes
  Check Char        1 byte
                  ---
                  274 bytes

No sector header is mentioned at all.


Page 9 "Counter 1G is the sector position counter" (admittedly a bit
vague, however on schematic page 3, we see counter 1G is reset by the
"index" hole signal, and clocked by the "new sector" signal (follow these
back to see how they are generated) - it's outputs are labled "Sector
Counter to 8080 via MPXR" - MPXR is IC 4E, a multiplexor which controls
Status A or B selected, which is the register read at $EB30 above.


I wrote my DMF OS originally on this system - since the controller ROM
vectors back to stubs at $2000, and DMF loads a 256 byte stub at $0000,
and the rest at the highest 4K block in the system (in my case $F000),
I could not use the controller ROM once the system booted - therefore
I wrote my own complete set of low-level disk access functions for the
NorthStar single-density controller.

I also simulated this controller right down to the hardware register
level with correct timing in my Altair/NorthStar simulator...

In other words - I know this controller AND system software VERY WELL -
there is NO sector header information written on the diskette.


Regards,
Dave
-- 
dave04a (at)    Dave Dunfield
dunfield (dot)  Firmware development services & tools: www.dunfield.com
com             Vintage computing equipment collector.
                http://www.parse.com/~ddunfield/museum/index.html


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