[sebhc] Re: Re-creating actual floppies from archive

[Dan Lanciani]

|It's been a long time, and I've forgotten the details. But I ran across
|it when I was designing the H-1000 (a replacement CPU board for the
|H89). The old 8250 had a bus fight problem with the Z80 at 4 MHz, and
|both new and old 8250 had problems at both 2 MHz and 4 MHz. National had
|an application note that outlined the problem.

When I got the H8-4 I still had an 8080 in my H8.  After Heath was
unwilling to replace more than one of the 8250s I found a couple
elsewhere that worked.  They could have been older or newer.  Later
I upgraded to a DG Z80 and the 8250s on the H8-4 continued to work,
though I rarely ran at 4.096MHz.  The Z80 did break my clever core
interface, though.  (It started a memory cycle before it knew whether
there was going to be a read or a write since the first half of the
core cycle was a destructive read in either case.  This was necessary
to run with 0 wait states on the 8080 which in turn was necessary for
the unmodified H17 code.)  How many people had core memory on their
H8s I wonder...

|When you compare the H89 and H89-A schematics, you'll see Heath added a
|74LS74 between the buffered read and write lines (/BRD and /BWR) and the
|8250's Data In Strobe (DISTR) and Data Out Strobe (/DOSTR) pins. My
|guess is that the 8250 was slow at taking its data off the bus during
|reads, and slow at latching its data in on writes. So they flip-flop was
|added to move the timing to avoid bus fights with the Z80.

Unfortunately, I gave away most of my H89 documentation.

				Dan Lanciani
				ddl at danlan.*com
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