[sebhc] list archive and a specific question

[Lee Hart]

Dan Lanciani wrote:
> ...the method used to synchronize the CPU with DRQ is very different.

Ok, pulling out the H8 schematics...

The H8 address and data buss happen to be inverted. No big deal; it
means there will need to be inverters between the H8 bus and S-100 bus
connector of the Z-100 disk controller board.

The H8 IOW and IOR (I/O Write and I/O Read strobes) are also inverted.
There may also need to be some timing control to match what the Z-100
board expects. I haven't looked at the Z-100 board's schematics yet.

> The Z100 controller uses the common approach of hanging the CPU's
> data port read/write until the controller is ready. The H8
> controller (if I'm remembering correctly) inserts itself between
> the bus and the interrupt instruction generator (the buffer that
> puts the RST n instruction on the bus) so it can push a NOP onto
> the bus after waking the CPU from an HLT used to wait for DRQ.
> The inner loop is just fast enough to handle 5.25" DD.

The H8 and H89 have the CPU execute a HALT instruction while waiting for
the next data byte from the H37 disk controller. When the byte is ready,
DRQ generates an interrupt, which frees the CPU from its HALT. The CPU
then reads the byte, saves it, increments the address counter, and loops
to do it all again for the next byte. This scheme is fast enough to
handle double-density 5.25" disks even with a 2 MHz 8080.

The Magnolia and CDR disk controllers used a different scheme, so they
could support 8" double-density formats. The H8 and H89 have the WAIT
line on their busses. When the CPU tries to read the next byte from the
disk controller, it gets held in the WAIT state until it is ready. This
saves a couple instruction times, making the loop fast enough to still
work with a 2 MHz 8080 or Z80.

Using HALT has the advantage that the Z80 maintains refresh of dynamic
memory in the H89. With WAIT, the H89's memory will crash if for some
reason the disk controller fails to provide the next byte in time.

The H8 uses static memory, so this isn't a problem. So, it looks like
the best solution for the Z-100 disk controller in an H8 is to use the
WAIT line. This avoids any need to alter the interrupt structure anyway.
-- 
If you would not be forgotten
When your body's dead and rotten
Then write of great deeds worth the reading
Or do the great deeds worth repeating
	-- Ben Franklin, Poor Richard's Almanac
--
Lee A. Hart, 814 8th Ave N, Sartell MN 56377, leeahart_at_earthlink.net

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